The fabrication of insulating wafers that can serve as carriers or substrates for electronic circuitry in which there are to be thousands of vias or through holes of micrometer dimensions that are completely filled with metal and have acceptable electrical impedance and electromigration performance is a subject of considerable importance in the electronic Industry. At the present state of electronic packaging there is generally a lower density of interconnection and wiring in most carriers and substrates than would be available with the integrated semiconductor chip technology. Intense study is taking place on the performance and design advantages of combining different circuitry types and organizations on a dense carrier or substrate with effort being directed to interface problems such as spacing mismatch and the difficulty of bringing signal and power lines in from peripheral supporting members. The technology is at times in the art referred to as System On Package (SOP) technology.
One example of effort in the field, is described in U.S. patent application Ser. No. 09/838,725 Filed Apr. 1, 1901 in which a structure is being contemplated where an interconnecting wafer supports multichip devices attached on one side, while on the opposite side of the wafer connections are made to other modules or boards with a different interconnection technology.
A discussion of the state of studies in the field appears in a 7 page technical article by J. Baliga, titled “Packaging Provides Viable Alternatives to SOC” in the publication “Semiconductor International” in July, 2000.
While much of the reported work is conducted on silicon about which much is known serving as the insulating wafer material, the parameters involved in the invention can readily be extended to other insulating materials; an example being work on the material glass which is reported in the 2001 IEEE Proceedings, pages 98-102 by Li et al titled “High Density Electrical Feedthroughs Fabricated by Deep Reactive Ion Etching of PYREX Glass”.
At the present state of the art however, many problems are being encountered as dimensions shrink into the sub 100 micrometer range, such as getting the dimensions of the via openings accurate and uniformly filled with metal yet being sufficiently structurally rigorous that the ability to use the Chemical Mechanical Polishing (CMP) type of processing which involves a combination of abrasion and chemical modifications, is preserved.